Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures

Most reconngurable multi-fpga architectures have a pro-grammable interconnection network that can be reconngured to implement diierent interconnection patterns between the fpgas and memory devices on the board. Partitioning tools for such architectures must produce the necessary pin-assignments and interconnect connguration stream that correctly implement the partitioned design. We call this process Interconnect Synthesis for reconngurable architectures. The primary contribution of this paper is a interconnection synthesis technique that is independent of the reconngurable interconnection architecture. We have developed an automatic interconnect synthesis tool that is based on Boolean satissability. The target interconnection architecture is modeled in an architecture speciication language. The desired interconnections among the fpgas are speciied as in the form of a netlist. The tool automatically generates the pin-assignments and the required values for the connguration-inputs in the architecture speciication. We modeled several reconngurable architectures and performed interconnect synthesis for varying number of desired nets. We provide experimental results that demonstrate the eeectiveness of the interconnection synthesis technique.